RFR: 8346478: RISC-V: Refactor add/sub assembler routines [v5]

[Fei Yang]

> Hi, please consider this cleanup change.
> 
> Currently, we have mixed use of `addi` and `add(int64_t)`/`sub(int64_t)`. The former adds a 12-bit immediate while the latter
> does not have a constraint on the immediate range. We should use `addi` when possible, which would help save one runtime check about the immediate range and avoid the use of one tmp register by the latter as well.
> 
> In order to make the code more readable, this also introduces helper routines `subi`/`subiw` and adapts callsites of `addi`/`addiw` with negative immediates.
> 
> 
> 
>  <Design of the RISC-V Instruction Set Architecture>:
> 
>  There is no SUBI instruction, because ADDI with a negative immediate is almost equivalent. The one
>  exception arises from the asymmetry of the twos complement representation: SUBI with an immediate of
>  211 would add 211 to a register, which ADDI is incapable of.
> 
> 
> Testing on Premier-P550 SBC running Ubuntu-24.04:
> - [x] : tier1-3 and gtest:all (release)
> - [x] : hotspot:tier1 (fastdebug)

Fei Yang has updated the pull request incrementally with one additional commit since the last revision:

  Revert unnecessary change

-------------

Changes:
  - all: https://git.openjdk.org/jdk/pull/22804/files
  - new: https://git.openjdk.org/jdk/pull/22804/files/b27fc623..55eaaac6

Webrevs:
 - full: https://webrevs.openjdk.org/?repo=jdk&pr=22804&range=04
 - incr: https://webrevs.openjdk.org/?repo=jdk&pr=22804&range=03-04

  Stats: 2 lines in 1 file changed: 0 ins; 0 del; 2 mod
  Patch: https://git.openjdk.org/jdk/pull/22804.diff
  Fetch: git fetch https://git.openjdk.org/jdk.git pull/22804/head:pull/22804

PR: https://git.openjdk.org/jdk/pull/22804