RFR: 8346478: RISC-V: Refactor add/sub assembler routines [v5]

[Fei Yang]

On Sun, 22 Dec 2024 12:34:24 GMT, Feilong Jiang <fjiang at openjdk.org> wrote:

>> Fei Yang has updated the pull request incrementally with one additional commit since the last revision:
>> 
>>   Revert unnecessary change
>
> src/hotspot/cpu/riscv/templateTable_riscv.cpp line 212:
> 
>> 210:   __ load_unsigned_byte(temp_reg, at_bcp(0));
>> 211:   __ beq(temp_reg, bc_reg, L_okay);
>> 212:   __ sub(temp_reg, temp_reg, (int)Bytecodes::java_code(bc));
> 
> ditto

Make sense. I have fixes all of them. Thanks.

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PR Review Comment: https://git.openjdk.org/jdk/pull/22804#discussion_r1895196662