RFR: 8346478: RISC-V: Refactor add/sub assembler routines [v6]

[Feilong Jiang]

On Mon, 23 Dec 2024 03:24:08 GMT, Fei Yang <fyang at openjdk.org> wrote:

>> Hi, please consider this cleanup change.
>> 
>> Currently, we have mixed use of `addi` and `add(int64_t)`/`sub(int64_t)`. The former adds a 12-bit immediate while the latter
>> does not have a constraint on the immediate range. We should use `addi` when possible, which would help save one runtime check about the immediate range and avoid the use of one tmp register by the latter as well.
>> 
>> In order to make the code more readable, this also introduces helper routines `subi`/`subiw` and adapts callsites of `addi`/`addiw` with negative immediates.
>> 
>> 
>> 
>>  <Design of the RISC-V Instruction Set Architecture>:
>> 
>>  There is no SUBI instruction, because ADDI with a negative immediate is almost equivalent. The one
>>  exception arises from the asymmetry of the twos complement representation: SUBI with an immediate of
>>  -2048 would add 2048 to a register, which ADDI is incapable of.
>> 
>> 
>> Testing on Premier-P550 SBC running Ubuntu-24.04:
>> - [x] : tier1-3 and gtest:all (release)
>> - [x] : hotspot:tier1 (fastdebug)
>
> Fei Yang has updated the pull request incrementally with one additional commit since the last revision:
> 
>   Review comments

Marked as reviewed by fjiang (Committer).

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PR Review: https://git.openjdk.org/jdk/pull/22804#pullrequestreview-2520628868