RFR: 8322179: RISC-V: Implement SHA-1 intrinsic [v8]

[Hamlin Li]

On Mon, 5 Feb 2024 06:01:51 GMT, Fei Yang <fyang at openjdk.org> wrote:

>> Hamlin Li has updated the pull request incrementally with one additional commit since the last revision:
>> 
>>   use x9 as src
>
> src/hotspot/cpu/riscv/stubGenerator_riscv.cpp line 4954:
> 
>> 4952:       __ add(cur_w, cur_k, cur_w);
>> 4953:       __ add(t, t, cur_w);
>> 4954:       __ rolw_imm(tmp1, a, 5, tmp2);
> 
> I am a bit concerned about the register usage here. I see the caller passes `t0` for `tmp1` and it's alive across `sha1_f` which is non-trivial. I think it could be error-prone since `t0` and `t1` are implictly used as temp registers by various assember functions. My suggestion is to remove `tmp1` and `tmp2` formal parameters and use both `t0` and `t1` directly in this function (and declare that this function will clobber both `t0` and `t1` in the preceding code comment). Then we can use the input `tmp3` here instead. Similar for `sha1_prepare_w` and `sha1_preserve_prev_abcde`. Could you please consider?

Updated, thanks!

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PR Review Comment: https://git.openjdk.org/jdk/pull/17130#discussion_r1477951621