RFR: 8324124: RISC-V: implement _vectorizedMismatch intrinsic

[Fei Yang]

On Wed, 7 Feb 2024 14:35:55 GMT, Yuri Gaevsky <duke at openjdk.org> wrote:

> Hello All,
> 
> Please review these changes to enable the __vectorizedMismatch_ intrinsic on RISC-V platform with RVV instructions supported.
> 
> Thank you,
> -Yuri Gaevsky
> 
> **Correctness checks:**
>   hotspot/jtreg/compiler/{intrinsic/c1/c2}/ under QEMU-8.1 with RVV v1.0.0 and -XX:TieredStopAtLevel=1/2/3/4.

src/hotspot/cpu/riscv/macroAssembler_riscv.cpp line 4256:

> 4254: 
> 4255:   bind(VEC_LOOP);
> 4256:   vsetvli(t0, cnt, Assembler::e8, Assembler::m8);

I see `e8` element size is always used here for all cases. Maybe we could make use of some larger element size (according to `log2_array_indxscale` input) to improve the code? Especiall, the part for handling `idx`.

-------------

PR Review Comment: https://git.openjdk.org/jdk/pull/17750#discussion_r1495640750