RFR: 8319716: RISC-V: Add SHA-2 [v10]

[Robbin Ehn]

On Wed, 3 Jan 2024 07:12:15 GMT, Robbin Ehn <rehn at openjdk.org> wrote:

>> src/hotspot/cpu/riscv/stubGenerator_riscv.cpp line 3792:
>> 
>>> 3790:                          Register scalarconst, VectorRegister vtemp, VectorRegister vtemp2, VectorRegister v_abef, VectorRegister v_cdgh,
>>> 3791:                          bool gen_words = true, bool step_const = true) {
>>> 3792:       __ vl1reXX_v(vset_sew, vtemp, scalarconst);
>> 
>> Shouldn't we use `vleXX_v` to load the constant for each round instead of `vl1reXX_v`? `vl1reXX_v` which delegates work to `vl1re32_v`/vl1re64_v only loads a single vector register and is not aware of the LMUL setting. I see the openssl version is using `vle32_v`/`vle64_v` to load 4 e32/e64 elements of the constants for each round.
>
> Thank you, this revealed an issue in my testing. qemu vlen setting was not properly set.
> As it should not have passed with 4xe64 with vlen 128.

Fixed

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PR Review Comment: https://git.openjdk.org/jdk/pull/16562#discussion_r1442604552