RFR: 8320069: RISC-V: Add Zcb instructions [v3]

[Robbin Ehn]

On Wed, 3 Jan 2024 06:08:26 GMT, Fei Yang <fyang at openjdk.org> wrote:

>> Robbin Ehn has updated the pull request with a new target base due to a merge or a rebase. The incremental webrev excludes the unrelated changes brought in by the merge/rebase. The pull request contains three additional commits since the last revision:
>> 
>>  - Merge branch 'master' into zcb
>>  - Merge branch 'master' into zcb
>>  - zcb instruction set
>
> src/hotspot/cpu/riscv/assembler_riscv.hpp line 542:
> 
>> 540:   INSN(_lbu, 0b0000011, 0b100); // Zcb
>> 541:   INSN(_lh,  0b0000011, 0b001); // Zcb
>> 542:   INSN(_lhu, 0b0000011, 0b101); // Zcb
> 
> The code comment for these three lines seems a bit misleading. These are normal 4-bytes encoding load/store instructions, not `Zcb` compressed instructions.

The comment was suppose to mean, these are 'overridden' by zcb, not C as the others.
I'll clarify that.

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PR Review Comment: https://git.openjdk.org/jdk/pull/17122#discussion_r1442650110