RFR: 8324186: Use "dmb.ishst+dmb.ishld" for release barrier [v4]

[kuaiwei]

On Tue, 23 Jan 2024 09:47:20 GMT, Andrew Haley <aph at openjdk.org> wrote:

>>> > I wonder if this was tested on other vendors' hardware? I witnessed some negative impact at least on HiSilicon TSV110 running the same JMH. So I guess it might be safer to go as a vendor-specific change.
>>> 
>>> I tried a number of different machines and saw regressions only on Kunpeng-920 (same CPU?) and A57 which is quite niche at this point.
>> 
>> @nick-arm : Thanks for trying it out. Yeah, TSV110 is the core micro-arch name for Kunpeng-920. @theRealAph : I don't have access to the details of TSV110 any more, I guess it's not easy to figure out what's going on :-(
>
>> > I wonder if this was tested on other vendors' hardware? I witnessed some negative impact at least on HiSilicon TSV110 running the same JMH. So I guess it might be safer to go as a vendor-specific change.
>> 
>> I tried a number of different machines and saw regressions only on Kunpeng-920 (same CPU?) and A57 which is quite niche at this point.
> 
> Right, so it's probably a low-end, mostly-in-order thing. That makes sense because we're trading a weaker barrier for more instructions, and perhaps some cores implement barriers in a crude one-size-fits-all way.

@theRealAph @RealFYang Could you help to sponsor it? Thanks

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PR Comment: https://git.openjdk.org/jdk/pull/17511#issuecomment-1913845465