RFR: 8332689: RISC-V: Use load instead of trampolines

[Andrew Haley]

On 5/29/24 15:28, Robbin Ehn wrote:
> On some CPUs L1D and L1I can't contain the same cache line, which means
> the tramopline stub can bounce from L1I->L1D->L1I, which is
> expensive.

Wouldn't it be a lot easier simply to put the target address loaded by the
trampoline into the constant pool?

> Even if you don't have that problem having a call to a jump is not the
> fastest way.

I guess the real problem there is that the jalr #imm range is pretty short,
so taking a trampoline is a very common case, and you have to optimize for
that. On AArch64 we optimize for the simple branch.

BTW, on AArch64 we don't have all the problems described in Zjid. For example,
if you modify code, do the icache invalidate dance, then patch a jump so that
it points to the newly-modified code, every observer sees the new code that was
modified before it sees the patched jump.

-- 
Andrew Haley  (he/him)
Java Platform Lead Engineer
Red Hat UK Ltd. <https://www.redhat.com>
https://keybase.io/andrewhaley
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