RFR: 8332689: RISC-V: Use load instead of trampolines [v10]

[Robbin Ehn]

On Wed, 12 Jun 2024 08:56:22 GMT, Hamlin Li <mli at openjdk.org> wrote:

>> Robbin Ehn has updated the pull request with a new target base due to a merge or a rebase. The pull request now contains 15 commits:
>> 
>>  - Merge branch 'master' into 8332689
>>  - Merge branch 'master' into 8332689
>>  - Merge branch 'master' into 8332689
>>  - Remove tmp file
>>  - Prepare for dynamic NativeCall size
>>  - Only allow one calling convetion, i.e. fixed sized
>>  - Merge branch 'master' into 8332689
>>  - Review comments
>>  - Move shart/far code to cpp
>>  - Cleanup
>>  - ... and 5 more: https://git.openjdk.org/jdk/compare/93f3918e...eb30360a
>
> src/hotspot/cpu/riscv/macroAssembler_riscv.cpp line 982:
> 
>> 980: 
>> 981: void MacroAssembler::load_link(const address source, Register temp) {
>> 982:   assert(temp != noreg && temp != x0, "expecting a register");
> 
> with `temp == x5`, this assert is redundant.
> A question, why require `temp == x5`?

No, reason, fixed.

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PR Review Comment: https://git.openjdk.org/jdk/pull/19453#discussion_r1642268548