RFR: 8329032: C2 compiler register allocation support for APX EGPRs [v6]

[Sandhya Viswanathan]

On Tue, 18 Jun 2024 16:17:57 GMT, Jatin Bhateja <jbhateja at openjdk.org> wrote:

>> Intel® Advanced Performance Extensions (Intel® APX) adds 16 new 64 bit general purpose register also known as Extended General Purpose Registers in IA-32e 64 bit mode.
>> 
>> Summary of changes introduced along with this patch:-
>> 
>> 1. C2 compiler register allocation support.
>> 2. Architecture state save restoration while transitioning from C1/C2 JIT compiled code to runtime services.
>> 3. Support new PUSH2/POP2 instructions along with push-pop acceleration hints (PPX) to optimize register save/restore operation.
>> 4. Applicable extensions to native interface used by runtime for patching instruction.
>> 
>> We plan to address C1 register support in subsequent patch as there are hard upper bound allocation limits
>> (currently set to r11) imposed by existing implementation of linear scan algorithm after which it reserves
>> remaining register for special purpose.
>> 
>> Patch has been regressed over stand alone test points after prioritizing EGPR allocations over existing GPR register by manually modifying the register sequences in relevant allocation class.
>> 
>> We plan to do thorough validation using [Intel's SDE](https://www.intel.com/content/www/us/en/download/684897/intel-software-development-emulator.html) during course of time and release incremental patches for bug fixes
>> found during testing.
>> 
>> Kindly review and share your feedback.
>> 
>> Best Regards,
>> Jatin
>
> Jatin Bhateja has updated the pull request with a new target base due to a merge or a rebase. The pull request now contains 14 commits:
> 
>  - Merge branch 'master' of http://github.com/openjdk/jdk into JDK-8329032
>  - 32-bit build fix.
>  - Review comments resolutions.
>  - jvmci test failures fixes
>  - 32-bit build fixes.
>  - Merge branch 'master' of http://github.com/openjdk/jdk into JDK-8329032
>  - Changes to skip over stack alignment gaps while popping registers using POP2 after comment from sviswa7
>  - 32 bit build fix and enforced stack alignment constraints.
>  - Support new PUSH2/POP2 instructions along with Push-Pop Acceleration (PPX) to optimize register save/restore operation.
>  - Merge branch 'master' of http://github.com/openjdk/jdk into JDK-8329032
>  - ... and 4 more: https://git.openjdk.org/jdk/compare/6f860f8f...8db22672

src/hotspot/cpu/x86/assembler_x86.cpp line 14315:

> 14313:     push2p(rbx, rdx);
> 14314:     // To maintain 16 byte alignment after rcx is pushed.
> 14315:     subq(rsp, 8);

Just curious, why do we need to maintain 16 byte alignment here? It looks to me that the subq(rsp, 8) is not required here. The next push is not a push2.

src/hotspot/cpu/x86/assembler_x86.cpp line 14327:

> 14325:     // from the value of rsp immediately after pusha (rsp + 16 * wordSize).
> 14326:     // FIXME: For APX any such direct access should also consider EGPR size
> 14327:     // during address compution.

This comment could be removed.

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PR Review Comment: https://git.openjdk.org/jdk/pull/19042#discussion_r1644799787
PR Review Comment: https://git.openjdk.org/jdk/pull/19042#discussion_r1644869780