RFR: 8320646: RISC-V: C2 VectorCastHF2F [v3]

[Fei Yang]

On Mon, 4 Mar 2024 11:52:54 GMT, Hamlin Li <mli at openjdk.org> wrote:

>> src/hotspot/cpu/riscv/c2_MacroAssembler_riscv.cpp line 2037:
>> 
>>> 2035:   __ mv(t0, 26);
>>> 2036:   // preserve the sign bit.
>>> 2037:   __ vnsra_wx(tmp, src, t0, Assembler::v0_t);
>> 
>> Will this more simpler version do here? `__ vnsra_wi(tmp, src, 26, Assembler::v0_t);`
>
> Seems not, as by vector spec, `vector-immediate | imm[4:0]` and `The value is sign-extended to SEW bits`, so maximum of imm should be 16-1.

Here is what I read from the RVV 1.0 spec [1]: 


The narrowing right shifts extract a smaller field from a wider operand and have both zero-extending (srl) and
sign-extending (sra) forms. The shift amount can come from a vector register group, or a scalar x register, or
a zero-extended 5-bit immediate. 

A zero-extended 5-bit immediate will have a maximum of 31. 

[1] https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#vector-narrowing-integer-right-shift-instructions

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PR Review Comment: https://git.openjdk.org/jdk/pull/17698#discussion_r1512091563