RFR: 8328878: Rework [AArch64] Use "dmb.ishst + dmb.ishld" for release barrier

[Andrew Haley]

On Mon, 25 Mar 2024 09:01:03 GMT, kuaiwei <duke at openjdk.org> wrote:

> > Are there any possible sequences of `dmb ld; dmb st` that will not be minimized?
> 
> The worst case is "dmb ld; dmb st; dmb ish", that will be merged as "dmb ld; dmb ish".

That's not too bad, I suppose, but to me it feels a little like unfinished business.

If I were you I'd accumulate `DMB`s as 3 bits (ld, st, and sy) and emit the Right Thing on the first non-DMB instruction. There's the interesting possibility that a DMB might be emitted as the last instruction before the end of the lifetime of an assembler. In that case I guess I'd do some experiments to find out what worked.

Also consider a queue? We already accumulate bits of an instruction in `Instruction_aarch64::bits`. Maybe that could be elaborated to defer `DMB` instructions?

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PR Comment: https://git.openjdk.org/jdk/pull/18467#issuecomment-2018225955