RFR: 8328878: Rework [AArch64] Use "dmb.ishst + dmb.ishld" for release barrier

[Andrew Haley]

On Mon, 25 Mar 2024 06:54:01 GMT, kuaiwei <duke at openjdk.org> wrote:

> The origin patch for https://bugs.openjdk.org/browse/JDK-8324186 has 2 issues:
> 1 It show regression in some platform, like Apple silicon in mac os
> 2 Can not handle instruction sequence like "dmb.ishld; dmb.ishst; dmb.ishld; dmb.ishld"
> 
> It can be fixed by:
> 1 Enable AlwaysMergeDMB by default, only disable it in architecture we can see performance improvement (N1 or N2)
> 2 Check the special pattern and merge the subsequent dmb.
> 
> It also fix a bug when code buffer is expanding, st/ld/dmb can not be merged. I added unit tests for these.
> 
> This patch still has a unhandled case. Insts like "dmb.ishld; dmb.ishst; dmb.ish", it will merge the last 2 instructions and can not merge all three. Because when emitting dmb.ish, if merge all previous dmbs, the code buffer will shrink the size. I think it may break some resumption and think it's not a common pattern.

Thinking some more, I've had a better idea. Consider a finite state machine. The states would perhaps be {pending_none, pending_ld, pending_st, pending_ldst}. Every `MacroAssembler::emit()`, along with `bind()`, advances the machine, and emits instructions on some state changes. This state machine would be used instead of  `code()->last_insn()`

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PR Comment: https://git.openjdk.org/jdk/pull/18467#issuecomment-2018433225