RFR: 8326306: RISC-V: Re-structure MASM calls and jumps [v10]

[Fei Yang]

On Mon, 13 May 2024 06:57:26 GMT, Robbin Ehn <rehn at openjdk.org> wrote:

>> src/hotspot/cpu/riscv/assembler_riscv.hpp line 2836:
>> 
>>> 2834:         Rd == x0 &&
>>> 2835:         is_simm12(offset) && ((offset % 2) == 0)) {
>>> 2836:       c_j(offset);
>> 
>> Is RV32C-only instructions usable for RV64C which is our case? Or will this if block be test covered?
>> 
>> The spec says:
>> 
>> In addition, RV32C includes a compressed jump and link instruction to compress
>> short-range subroutine calls, where the same opcode is used to compress ADDIW for RV64C and
>> RV128C.
>
> There are two instructions using the CJ format: c.j and c.jal.
> - c.j is already in our assembler.
> - c.jal is not in our assembler and is RV32C only.
> 
> 
> 000000000000064e <c_j>:
>      64e: 11 a0        	j	0x652 <c_j+0x4>  // 0xa011 is c.j 4
>      650: 2a 85        	mv	a0, a0
>      652: 82 80        	ret
> 
> 
> Works fine on both VF2 and qemu-rv64.
> 
> The comment was just saying that we can't try to map to c.jal since it's RV32C.
> 
> The instruction c.j have the same test coverage as before (as we already have it in assembler).
> The toogle to C I think is untested as it only can be generated for short backwards branches in non-relocated code.
> 
> As the comment is obvious confusing, suggestions to change it?

Uh, I see. I think I mis-read the code comment. I am OK with the current shape.

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PR Review Comment: https://git.openjdk.org/jdk/pull/18942#discussion_r1597985825