RFR: 8332265: RISC-V: Materialize pointers faster by using a temp register [v5]

[Ludovic Henry]

On Wed, 22 May 2024 18:41:16 GMT, Robbin Ehn <rehn at openjdk.org> wrote:

>> Hi, please consider!
>> 
>> Materializing a 48-bit pointer, using an additional register, we can do with:
>> lui + lui + slli + add + addi
>> This 15% faster both on VF2 and in CPU models, compared to movptr().
>> 
>> As we often materialize during calls there is free registers.
>> 
>> I have choose just a few spot to use it, many more can use.
>> E.g. la() with tmp register can use li48 instead of movptr.
>> 
>> Running tests now (so far so good), as if I screwed up IC calls it should be seen fast.
>> And benchmarks when hardware is free.
>
> Robbin Ehn has updated the pull request with a new target base due to a merge or a rebase. The pull request now contains ten commits:
> 
>  - Merge branch 'master' into 8332265
>  - More review comments
>  - Review changes
>  - Merge branch 'master' into 8332265
>  - Merge branch 'master' into 8332265
>  - Small review update
>  - li48 -> movptr
>  - Merge branch 'master' into 8332265
>  - li48

src/hotspot/cpu/riscv/macroAssembler_riscv.cpp line 3734:

> 3732: 
> 3733: int MacroAssembler::static_call_stub_size() {
> 3734:   // (lui, addi, slli, addi, slli, addi) + (lui + lui + ssli + add) + jalr

Instead of `ssli`, shouldn't it be `slli`?

src/hotspot/cpu/riscv/nativeInst_riscv.hpp line 402:

> 400:     } else if (is_movptr2_at(instruction_address())) {
> 401:       if (is_addi_at(addr_at(movptr2_instruction_size - NativeInstruction::instruction_size))) {
> 402:         // Assume: lui, addi, slli, addi, slli, addi

If it's a `movptr2` here, the `Assume: lui, addi, slli, addi, slli, addi` comment seems wrong. Same at https://github.com/openjdk/jdk/pull/19246/files#diff-cadab323d5b577bec017d8ed262bff9d2318e38c0a62afe567050e86ff62cbb9R405

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PR Review Comment: https://git.openjdk.org/jdk/pull/19246#discussion_r1611455331
PR Review Comment: https://git.openjdk.org/jdk/pull/19246#discussion_r1611459701