RFR: 8332900: RISC-V: refactor nativeInst_riscv.cpp and macroAssembler_riscv.cpp [v3]

[Fei Yang]

On Fri, 31 May 2024 07:53:45 GMT, Hamlin Li <mli at openjdk.org> wrote:

> > There will surely be some protocols between the them under the hood.
> 
> If this protocol means lots of dual direction communication, then we should consider if it's right (from a point of view OO design, it's an obvious code smell for me). NativeInstruction could be a wrapper upon MacroAssembler, but not in reverse direction, in that way it makes things complicated and it's not necessary and bring no benefit.

I guess that might deserve a broader discussion as it does not seem to be a RISC-V specific issue.

> > BTW: this is also adopted by other CPUs like aarch64.
> 
> Yes, we can refer or copy some code from other platforms in case they're well implemented. Please check https://github.com/openjdk/jdk/blob/master/src/hotspot/cpu/aarch64/nativeInst_aarch64.hpp#L137, the `extract` is not in nativeInst_aarch64, it's in assembler_aarch64.

The RISC-V counter part: https://github.com/openjdk/jdk/blob/master/src/hotspot/cpu/riscv/assembler_riscv.hpp#L384

The protocol is also there for aarch64 (movptr as an example): https://github.com/openjdk/jdk/blob/master/src/hotspot/cpu/aarch64/nativeInst_aarch64.hpp#L290

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PR Comment: https://git.openjdk.org/jdk/pull/19459#issuecomment-2141454177