RFR: 8345047: RISC-V: Remove explicit use of AvoidUnalignedAccesses in interpreter

[Hamlin Li]

On Tue, 26 Nov 2024 10:19:40 GMT, Fei Yang <fyang at openjdk.org> wrote:

> Hi, please consider this small interpreter cleanup change.
> 
> The use of `AvoidUnalignedAccesses` option for these cases doen't much sense to me.
> MacroAssembler routines like `revb_h_h_u` and `revb_h_h` will emit 5 instructions when Zbb extension is not available. This is more than the case when `AvoidUnalignedAccesses` option is true. After this change, we always emit 4 instructions compared to 3 instructions in the case when we have Zbb extension. But I don't think it will make a difference.
> 
> Testing on linux-riscv64 platform:
> - [x] tier1 (release)

Thanks for improving the code.
Just some minor comments.

src/hotspot/cpu/riscv/interp_masm_riscv.cpp line 182:

> 180: void InterpreterMacroAssembler::get_unsigned_2_byte_index_at_bcp(Register reg, int bcp_offset) {
> 181:   assert(bcp_offset >= 0, "bcp is still pointing to start of bytecode");
> 182:   lbu(t1, Address(xbcp, bcp_offset));

maybe we could expand the revb_h_h here? something like below:

if ((AvoidUnalignedAccesses && (bcp_offset % 2)) || !UseZbb) {
  ...
} else {
  // expand revb_h_h_u when +UseZbb
}

src/hotspot/cpu/riscv/interp_masm_riscv.cpp line 198:

> 196:   assert(bcp_offset > 0, "bcp is still pointing to start of bytecode");
> 197:   if (index_size == sizeof(u2)) {
> 198:     load_short_misaligned(index, Address(xbcp, bcp_offset), tmp, false);

This change looks good.

-------------

PR Review: https://git.openjdk.org/jdk/pull/22387#pullrequestreview-2461117612
PR Review Comment: https://git.openjdk.org/jdk/pull/22387#discussion_r1858263265
PR Review Comment: https://git.openjdk.org/jdk/pull/22387#discussion_r1858264253