RFR: 8345110: RISC-V: Optimize and and clean up byte reverse assembler routine

[Fei Yang]

Hi, Could you please help review this change?

MacroAssembler routines `revb_w` and `revb_w_w` will emit 32 and 17 instructions respectively without Zbb.

Major changes:
1. There is no need for `revb_w` to reverse bytes for each 32-bit word.
   All the callers only care about the lower 32-bit word. This reimplement `revb_w` so that it only
   reverses bytes in lower 32-bit word and sign-extends the result (14 instructions). This makes `revb_w_w` duplicate.
2. Removed some assembler routines that are unused or become unnecessary (`revb_h`, `revb_h_helper`, `revb_h_h`, `revb_w_w`).
3. Adapted callers of these removed assembler routines in file `riscv_b.ad` to emit Zbb instructions directly.

Will look into `revb_h_h_u` and `revb_h_w_u` after this change.

Testing on linux-riscv64 platform:
- [ ] tier1 (release)

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Commit messages:
 - 8345110: RISC-V: Optimize and and clean up byte reverse assembler routine

Changes: https://git.openjdk.org/jdk/pull/22410/files
  Webrev: https://webrevs.openjdk.org/?repo=jdk&pr=22410&range=00
  Issue: https://bugs.openjdk.org/browse/JDK-8345110
  Stats: 122 lines in 4 files changed: 23 ins; 77 del; 22 mod
  Patch: https://git.openjdk.org/jdk/pull/22410.diff
  Fetch: git fetch https://git.openjdk.org/jdk.git pull/22410/head:pull/22410

PR: https://git.openjdk.org/jdk/pull/22410