RFR: 8339573: Update CodeCacheSegmentSize and CodeEntryAlignment for ARM [v3]

[Vladimir Kozlov]

On Wed, 9 Oct 2024 14:59:08 GMT, Boris Ulasevich <bulasevich at openjdk.org> wrote:

>> The behavior remains unchanged when replacing the NOP with an ADD x1,x1,x1 instruction. That said, I fully agree with you that the benchmark is peculiar, and the result doesn't necessarily indicate whether the platform is sensitive to code entry alignment. Additionally, I'd like to point out that on the same N1 platform, EEMBC's CoreMark benchmark runs 0.07% faster (a small difference, I know) on G2 when built with -falign-functions=64 compared to -falign-functions=16, with the result for -falign-functions=32 falling in between. This makes me doubt that CodeEntryAlignment=16/32 is reasonable for N1.
>> 
>> Let me ask Vladimir if it is possible to check the performance with CodeEntryAlignment=32 setting.
>
> Dear @vnkozlov,
> Sorry for bothering you. Is it possible to check if CodeEntryAlignment=32 setting causes the regression on Ampere system with the internal benchmark?

Okay

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PR Review Comment: https://git.openjdk.org/jdk/pull/20864#discussion_r1793906804