RFR: 8340241: RISC-V: Returns mispredicted [v2]

[Robbin Ehn]

On Mon, 14 Oct 2024 02:51:56 GMT, Fei Yang <fyang at openjdk.org> wrote:

>> Robbin Ehn has updated the pull request incrementally with one additional commit since the last revision:
>> 
>>   Fixed return should be done with RA by using RET mnemonic
>
> src/hotspot/cpu/riscv/gc/z/zBarrierSetAssembler_riscv.cpp line 729:
> 
>> 727:     __ mv(t1, stub->slow_path());
>> 728:     __ jalr(t1);
>> 729:   }
> 
> Bad news is that I do notice problems with use of t1 register for C2 rflags. Similar issue already exists for JDK head.
> See this PR for more details: https://github.com/openjdk/jdk/pull/21485. I think we should get this resolved before this one.

Yes, thanks!

> src/hotspot/cpu/riscv/stubGenerator_riscv.cpp line 1192:
> 
>> 1190:     Label L_continue;
>> 1191:     __ bltu(t0, t1, L_continue);
>> 1192:     __ j(nooverlap_target, t1);
> 
> Can we make use of the default param `t1`?
> 
>   void j(const address dest, Register temp = t1);
>   void j(const Address &adr, Register temp = t1);

Yes, we can, but in some cases the use of t1 is not obvious therefore I was unsure if I should make t1 default or not.
I'll change then.

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PR Review Comment: https://git.openjdk.org/jdk/pull/21406#discussion_r1799137215
PR Review Comment: https://git.openjdk.org/jdk/pull/21406#discussion_r1799138389