RFR: 8340241: RISC-V: Returns mispredicted [v12]

[Robbin Ehn]

On Tue, 15 Oct 2024 11:26:18 GMT, Fei Yang <fyang at openjdk.org> wrote:

>> Robbin Ehn has updated the pull request with a new target base due to a merge or a rebase. The incremental webrev excludes the unrelated changes brought in by the merge/rebase. The pull request contains 15 additional commits since the last revision:
>> 
>>  - Merge branch 'master' into remove_t0
>>  - ICData move to t1, removed dead code
>>  - Revert clinit_barrier
>>  - Fixed no explicit use of default t1
>>  - Revert clinit_barrier t1
>>  - Upstream comment
>>  - Fixed no explicit use of default t1
>>  - Merge branch 'master' into remove_t0
>>  - Another one removing explicit use of default t1
>>  - Updated assert
>>  - ... and 5 more: https://git.openjdk.org/jdk/compare/738fa89e...c95c9601
>
> src/hotspot/cpu/riscv/c1_CodeStubs_riscv.cpp line 97:
> 
>> 95:   // t0 and t1 are used as args in generate_exception_throw，
>> 96:   // so use x9 as the tmp register for rt_call.
>> 97:   __ rt_call(Runtime1::entry_for(stub_id), x9);
> 
> Not sure if `x9` is usable for us here after another look. Seems all registers must be preserved from the code comment [1]. We need to double check.
> 
> [1] https://github.com/openjdk/jdk/blob/master/src/hotspot/cpu/x86/c1_CodeStubs_x86.cpp#L130

As we are throwing an exception we get away with it in this case. (as in no test failures)
I was expecting that maybe some test would see it, as it maybe observable in some cases, but no test fails due to it. And then forgot about it :) 

As C1 only have a subset of registers available to the allocator we could use maybe use on of those to not override a local value which may be in the oopmap?

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PR Review Comment: https://git.openjdk.org/jdk/pull/21406#discussion_r1801616872