RFR: 8340241: RISC-V: Returns mispredicted [v12]

[Robbin Ehn]

On Tue, 15 Oct 2024 10:49:15 GMT, Fei Yang <fyang at openjdk.org> wrote:

>> Robbin Ehn has updated the pull request with a new target base due to a merge or a rebase. The incremental webrev excludes the unrelated changes brought in by the merge/rebase. The pull request contains 15 additional commits since the last revision:
>> 
>>  - Merge branch 'master' into remove_t0
>>  - ICData move to t1, removed dead code
>>  - Revert clinit_barrier
>>  - Fixed no explicit use of default t1
>>  - Revert clinit_barrier t1
>>  - Upstream comment
>>  - Fixed no explicit use of default t1
>>  - Merge branch 'master' into remove_t0
>>  - Another one removing explicit use of default t1
>>  - Updated assert
>>  - ... and 5 more: https://git.openjdk.org/jdk/compare/c39b6f3c...c95c9601
>
> src/hotspot/cpu/riscv/assembler_riscv.hpp line 2895:
> 
>> 2893: // --------------------------
>> 2894:  protected:
>> 2895:   // All calls and jumps must go via MASM.
> 
> Better to add some extra code comment here about the link register usage. Say:
> 
> // All calls and jumps must go via MASM. Only use x1 (aka ra) as link register for now.

Fixed

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PR Review Comment: https://git.openjdk.org/jdk/pull/21406#discussion_r1801654493