RFR: 8340241: RISC-V: Returns mispredicted [v10]

[Robbin Ehn]

On Tue, 15 Oct 2024 06:27:37 GMT, Fei Yang <fyang at openjdk.org> wrote:

>> Robbin Ehn has updated the pull request incrementally with two additional commits since the last revision:
>> 
>>  - Fixed no explicit use of default t1
>>  - Revert clinit_barrier t1
>
> src/hotspot/cpu/riscv/macroAssembler_riscv.cpp line 771:
> 
>> 769:                                        Label *retaddr) {
>> 770:   int32_t offset = 0;
>> 771:   push_reg(RegSet::of(t1, xmethod), sp);   // push << t0 & xmethod >> to sp
> 
> Code comment needs update.

Fixed

> src/hotspot/cpu/riscv/macroAssembler_riscv.cpp line 777:
> 
>> 775:     bind(*retaddr);
>> 776:   }
>> 777:   pop_reg(RegSet::of(t1, xmethod), sp);   // pop << t0 & xmethod >> from sp
> 
> Code comment needs update.

Fixed

-------------

PR Review Comment: https://git.openjdk.org/jdk/pull/21406#discussion_r1801654874
PR Review Comment: https://git.openjdk.org/jdk/pull/21406#discussion_r1801654658