RFR: 8340241: RISC-V: Returns mispredicted [v15]

[Fei Yang]

On Wed, 16 Oct 2024 12:22:23 GMT, Robbin Ehn <rehn at openjdk.org> wrote:

>> src/hotspot/cpu/riscv/macroAssembler_riscv.cpp line 4082:
>> 
>>> 4080:                                                    Register tmp2,
>>> 4081:                                                    Register tmp3) {
>>> 4082:   assert_different_registers(r_sub_klass, r_super_klass, tmp1, tmp2, tmp3, result, t0, t1);
>> 
>> This `MacroAssembler::verify_secondary_supers_table` is used by `MacroAssembler::lookup_secondary_supers_table` which is called by C2 `instruct partialSubtypeCheckConstSuper` in riscv.ad. We should list the rflags (aka t1) as being killed for this instruct as well. As this is not obvious, we need to double check if there are other similar occurrences like this.
>
> Same anwser here actual call do not need to kill CR as RFLAG is SOC.

Note that C2 instruct `partialSubtypeCheckConstSuper` is not a call. So this issue is still there for this case I think. 
(Also `t0` and `t1` is reserved from C2, so I don't think they will save and restore them. That's why we add clobbering for `t1`/rflags for C2 calling instructs: CallRuntime/CallDynamicJava ...)

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PR Review Comment: https://git.openjdk.org/jdk/pull/21406#discussion_r1803018392