RFR: 8339790: Support Intel APX setzucc instruction [v2]

[Andrew Haley]

On Tue, 10 Sep 2024 11:45:25 GMT, Jatin Bhateja <jbhateja at openjdk.org> wrote:

>> - Support APX variant of SETcc, which supports zero-upper semantics (full register writer). Sets the destination operand to 0 or 1 depending on the settings of the status flags (CF, SF, OF, ZF, and PF) in the EFLAGS register. The destination operand points to a byte register or a byte in memory. The
>> condition code suffix (cc) indicates the condition being tested for. Additionally, if ND = 1 and the destination is a GPR, then also set the upper 56 bits of the GPR to 0.
>> - This saves emitting an explicit MOVZX instruction after setCC.
>> - These new instructions are encoded using 4 byte Extended EVEX encoding.
>> 
>> Validation performed over stand alone test point using Intel SDE.
>> 
>> Best Regards,
>> Jatin
>
> Jatin Bhateja has updated the pull request incrementally with one additional commit since the last revision:
> 
>   Review resolutions.

src/hotspot/cpu/x86/x86_64.ad line 7095:

> 7093:             "sete    $res\n\t"
> 7094:             "movzbl  $res, $res" %}
> 7095:   ins_encode %{

Maybe change the format statement to match.

-------------

PR Review Comment: https://git.openjdk.org/jdk/pull/20920#discussion_r1752157139