RFR: 8339790: Support Intel APX setzucc instruction [v4]

[Jatin Bhateja]

On Mon, 16 Sep 2024 18:17:44 GMT, Sandhya Viswanathan <sviswanathan at openjdk.org> wrote:

>> Jatin Bhateja has updated the pull request incrementally with one additional commit since the last revision:
>> 
>>   Review comments resolution.
>
> src/hotspot/cpu/x86/assembler_x86.cpp line 16052:
> 
>> 16050: 
>> 16051:   // Encoding Format : eevex_prefix | opcode_cc | modrm
>> 16052:   int encode = vex_prefix_and_encode(dst->encoding(), 0, 0, VEX_SIMD_F2, /* MAP4 */VEX_OPCODE_0F_3C, &attributes);
> 
> We could replace this with:
> int encode = evex_prefix_and_encode_ndd(dst->encoding(), 0, 0, VEX_SIMD_F2, /* MAP4 */VEX_OPCODE_0F_3C, &attributes);

Zero upper setCC repurpose the NDD bit which is always set by default.

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PR Review Comment: https://git.openjdk.org/jdk/pull/20920#discussion_r1762273655