RFR: 8351949: RISC-V: Cleanup and enable store-load peephole for membars [v8]

[Fei Yang]

On Thu, 3 Apr 2025 10:44:07 GMT, Hamlin Li <mli at openjdk.org> wrote:

>>> @feilongjiang and @RealFYang what do you think ?
>> 
>> Interesting :-) Supposing that they are subject to change (maybe possible further optimizations for specific memory model) in the future, I personally perfer a clean separation of the type types. And I guess it's more likely that people will only look at one of them at a time.
>
> Seems we should only consider current code base, and not consider possible optimization in the future? : )
> I'm not objecting current change, it's fine to me too.

Another concern from myside is that the RISC-V ISA is still evolving. People are working on Load-Acquire & Store-Release (Check RISC-V Zalasr extension [[1]](https://github.com/riscv/riscv-zalasr)). From my knowledge on aarch64's support for ldar/stlr instructions, I am expecting quite some change in the WMO part when we have such a similar extension. But I don't think that the TSO part will be affected much. So better to decouple the two for now.

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PR Review Comment: https://git.openjdk.org/jdk/pull/24035#discussion_r2026759091