RFR: 8351666: [PPC64] Make non-volatile VectorRegisters available for C2 register allocation [v4]

[Richard Reingruber]

On Wed, 9 Apr 2025 10:40:16 GMT, Richard Reingruber <rrich at openjdk.org> wrote:

>> Martin Doerr has updated the pull request incrementally with one additional commit since the last revision:
>> 
>>   Update Copyright header.
>
> src/hotspot/cpu/ppc/ppc.ad line 261:
> 
>> 259: // ----------------------------
>> 260:   // 1st 32 VSRs are aliases for the FPRs which are already defined above.
>> 261:   reg_def VSR0   (SOC, SOC, Op_VecX, 0, VMRegImpl::Bad());
> 
> I wonder how the old reg_defs worked, e.g. when allocating spill slots. Do you know?
> BTW: You might use vector pair load/stores in `MachSpillCopyNode::implementation()` too.

Ah, I see: it depends on Op_VecX. Op_VecX has 4 slots: https://github.com/openjdk/jdk/blob/7aeaa3c21c1420191fe8ff59e4cf99eae830754d/src/hotspot/share/opto/regmask.hpp#L90-L110

Hm, is it really necessary to model the vector registers as 4 32-bit parts? As you said offline this makes the `RegisterMasks` larger. If so then shouldn't Op_VecS be used?

> src/hotspot/cpu/ppc/stubGenerator_ppc.cpp line 220:
> 
>> 218:       BLOCK_COMMENT("Call frame manager or native entry.");
>> 219:       // Call frame manager or native entry.
>> 220:       assert_different_registers(r_arg_entry, r_top_of_arguments_addr, r_arg_method, r_arg_thread);
> 
> Since you're at it: please adjust the 2 comment lines above: there's no frame manager. We're about to call the interpreter or native entry.
> Also L222 (just remove "on entry ..."), L245. L265

Alternatively create a cleanup RFE for the stale "frame manager" comments.

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PR Review Comment: https://git.openjdk.org/jdk/pull/23987#discussion_r2035153598
PR Review Comment: https://git.openjdk.org/jdk/pull/23987#discussion_r2035814736