RFR: 8353558: x86: Use better instructions for ICache sync when available [v3]

[Aleksey Shipilev]

> For Leyden, that wants to load a lot of code as fast as it can, code cache flush costs are now significant part of the picture. There are single-digit percent startup time opportunities in better ICache syncs.
> 
> It is not sufficiently clear why icache flushes are needed for x86. Intel/AMD manuals say the instruction caches are fully coherent. GCC intrinsic for `__builtin___clear_cache` is empty. It looks that a single serializing instruction like `cpuid` might be OK for the entire flush to happen, this is what our `OrderAccess::cross_modify_fence` does. Still, we can maintain the old behavior by flushing the caches smarter: there are CLFLUSHOPT and CLWB available on modern x86.
> 
> See more discussion and references in the RFE. The performance data is in the comments in this PR.
> 
> Additional testing:
>  - [x] Linux x86_64 server fastdebug, `all`
>  - [x] Linux x86_64 server fastdebug, `all` + `X86ICacheSync={0,1,2,3,4}`

Aleksey Shipilev has updated the pull request incrementally with one additional commit since the last revision:

  Add SERIALIZE as well

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Changes:
  - all: https://git.openjdk.org/jdk/pull/24389/files
  - new: https://git.openjdk.org/jdk/pull/24389/files/c52e8074..711d7eac

Webrevs:
 - full: https://webrevs.openjdk.org/?repo=jdk&pr=24389&range=02
 - incr: https://webrevs.openjdk.org/?repo=jdk&pr=24389&range=01-02

  Stats: 20 lines in 5 files changed: 17 ins; 0 del; 3 mod
  Patch: https://git.openjdk.org/jdk/pull/24389.diff
  Fetch: git fetch https://git.openjdk.org/jdk.git pull/24389/head:pull/24389

PR: https://git.openjdk.org/jdk/pull/24389