RFR: 8353558: x86: Use better instructions for ICache sync when available [v2]

[Aleksey Shipilev]

On Tue, 15 Apr 2025 11:18:00 GMT, Quan Anh Mai <qamai at openjdk.org> wrote:

>> Aleksey Shipilev has updated the pull request with a new target base due to a merge or a rebase. The incremental webrev excludes the unrelated changes brought in by the merge/rebase. The pull request contains one additional commit since the last revision:
>> 
>>   Fix
>
> src/hotspot/cpu/x86/icache_x86.cpp line 42:
> 
>> 40:       break;
>> 41:     case 4:
>> 42:       __ push(rax);
> 
> x86 also has `serialize` which does, you guess what, serialize the instruction stream. I suggest adding a routine in `MacroAssembler` which does this if `serialize` is not available.
> 
> https://www.felixcloutier.com/x86/serialize

Right, we can throw `SERIALIZE` in the mix as well, at very least to match what `OrderAccess::cross_modify_fence` is doing. I believe it is cleaner to map it to another mode, rather than opting-in automatically. See new commit.

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PR Review Comment: https://git.openjdk.org/jdk/pull/24389#discussion_r2044459926