RFR: 8353558: x86: Use better instructions for ICache sync when available [v3]

Vladimir Kozlov kvn at openjdk.org
Thu Apr 17 18:19:46 UTC 2025


On Tue, 15 Apr 2025 12:56:37 GMT, Aleksey Shipilev <shade at openjdk.org> wrote:

>> For Leyden, that wants to load a lot of code as fast as it can, code cache flush costs are now significant part of the picture. There are single-digit percent startup time opportunities in better ICache syncs.
>> 
>> It is not sufficiently clear why icache flushes are needed for x86. Intel/AMD manuals say the instruction caches are fully coherent. GCC intrinsic for `__builtin___clear_cache` is empty. It looks that a single serializing instruction like `cpuid` might be OK for the entire flush to happen, this is what our `OrderAccess::cross_modify_fence` does. Still, we can maintain the old behavior by flushing the caches smarter: there are CLFLUSHOPT and CLWB available on modern x86.
>> 
>> See more discussion and references in the RFE. The performance data is in the comments in this PR.
>> 
>> Additional testing:
>>  - [x] Linux x86_64 server fastdebug, `all`
>>  - [x] Linux x86_64 server fastdebug, `all` + `X86ICacheSync={0,1,2,3,4}`
>
> Aleksey Shipilev has updated the pull request incrementally with one additional commit since the last revision:
> 
>   Add SERIALIZE as well

Is this assignment atomic? It is in `ICacheStubGenerator::generate_icache_flush()`:

*flush_icache_stub = (ICache::flush_icache_stub_t)start;

-------------

PR Review: https://git.openjdk.org/jdk/pull/24389#pullrequestreview-2776582762


More information about the hotspot-dev mailing list