RFR: 8351666: [PPC64] Make non-volatile VectorRegisters available for C2 register allocation [v17]

[Martin Doerr]

On Tue, 22 Apr 2025 14:48:01 GMT, Richard Reingruber <rrich at openjdk.org> wrote:

>> Martin Doerr has updated the pull request with a new target base due to a merge or a rebase. The incremental webrev excludes the unrelated changes brought in by the merge/rebase. The pull request contains 26 additional commits since the last revision:
>> 
>>  - Merge remote-tracking branch 'origin' into 8351666_PPC64_nv_VRs
>>  - C1: Avoid set_callee_saved for high halves like in sharedRuntime RegisterSaver.
>>  - Fix regName for VSR VMRegs.
>>  - Support displacement for new load/storeV16_Power9 nodes.
>>  - Fix OopMap for Power10 Little Endian.
>>  - Use consistent vector element ordering and simplify OopMap code.
>>  - Handle alignment.
>>  - Change VSR reg_defs to Op_RegF.
>>  - Improve VMReg handling.
>>  - Handle alignment.
>>  - ... and 16 more: https://git.openjdk.org/jdk/compare/0bead8ff...5168c5b8
>
> src/hotspot/cpu/ppc/sharedRuntime_ppc.cpp line 256:
> 
>> 254:   RegisterSaver_LiveVSReg( VSR59 ),
>> 255:   RegisterSaver_LiveVSReg( VSR60 ),
>> 256:   RegisterSaver_LiveVSReg( VSR61 )
> 
> What about VSR62 and VSR63?

Fixed. Thanks!

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PR Review Comment: https://git.openjdk.org/jdk/pull/23987#discussion_r2054338483