RFR: 8351666: [PPC64] Make non-volatile VectorRegisters available for C2 register allocation [v4]

[Andrew Haley]

On Fri, 11 Apr 2025 20:18:35 GMT, Martin Doerr <mdoerr at openjdk.org> wrote:

>>> Better instructions are now used on Power9/10.
>> 👍
>> 
>>> VSR0-31 removal has caused issues like "fatal error: Not compilable at tier 4: unsupported outgoing calling sequence". I've added them back. I'll take another look.
>> 
>> I see. Thanks for trying. I'd be ok with creating a separate RFE for that task.
>> You should investigate though the number of spill slots used for a vector register. Reading the comments (see link in previous comment) my understanding is that with `Op_VecX` and `SlotsPerVecX = 4` it might be 4 x 4 slots (16 x 4 = 64 bytes) but only 4 slots (16 bytes) are needed.
>
> Good catch! I had forgotten to replace `Op_VecX`. I'm using `Op_RegF`, now.

The comments in HotSpot make it clear that VMRegs are 4 bytes wide on all platforms, and stack slots are the size of VMRegs, and physical registers are modelled as some number of VMRegs. I never knew how PPC worked before.

> Hm, is it really necessary to model the vector registers as 4 32-bit parts?

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PR Review Comment: https://git.openjdk.org/jdk/pull/23987#discussion_r2055913863