RFR: 8365147: AArch64: Replace DMB + LD + DMB with LDAR for C1 volatile field loads

[Andrew Haley]

On Tue, 12 Aug 2025 14:59:40 GMT, Samuel Chee <duke at openjdk.org> wrote:

> Replaces the DMB ISH + LD + DMB ISHLD sequence with LDAR for volatile field loads - for example, AtomicLong::get.
> 
> This is valid, as originally the DMBs were necessary due to the case described here - https://bugs.openjdk.org/browse/JDK-8179954. As in the rare case where the LD can be reordered with an LDAR or STLR from the C2 implementation for stores and loads, these DMBs are required.
> However, acquire/release operations use a sequentially consistent model which does not allow reordering between them. Hence, the LD can be replaced with an LDAR to disallow reordering with a STLR/LDAR and the first DMB can be removed.
> 
> The LDAR has acquire semantics, so it's impossible for memory accesses after to be reordered before; the DMB ISHLD is not required. Therefore, a singular LDAR is sufficient.
> 
> This excludes floats and doubles, as they do not have equivalent load-acquire instructions.

src/hotspot/cpu/aarch64/c1_LIRAssembler_aarch64.cpp line 917:

> 915:                                      LIR_PatchCode patch_code, CodeEmitInfo* info) {
> 916:   if (is_floating_point_type(type)) {
> 917:     // Use LDAR instead of DMB+LD+DMB, except for floats/doubles (no LDAR equivalent).

We need more information here. If we're using LDAR, we should `ldar x8, mem; movd dest, x8`

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PR Review Comment: https://git.openjdk.org/jdk/pull/26748#discussion_r2270232188