RFR: 8345125: Aarch64: Add aarch64 backend for Float16 scalar operations [v2]

[Hao Sun]

On Tue, 25 Feb 2025 19:45:31 GMT, Bhavana Kilambi <bkilambi at openjdk.org> wrote:

>> This patch adds aarch64 backend for scalar FP16 operations namely - add, subtract, multiply, divide, fma, sqrt, min and max.
>
> Bhavana Kilambi has updated the pull request incrementally with one additional commit since the last revision:
> 
>   Address review comments

src/hotspot/cpu/aarch64/assembler_aarch64.hpp line 2097:

> 2095: 
> 2096:   // Half-precision floating-point instructions
> 2097:   INSN(fabdh,  0b011, 0b11, 0b000101, 0b0);

I suppose `fadbh` and `fnmulh` are added to keep aligned with the float and double ones, i.e. `fabd(s|d)` and `fnmul(s|d)`.


I noticed that there are matching rules for `fabd(s|d)`, i.e. `absd(F|D)_reg`. I wonder if we need add the corresponding rule for fp16 here?

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PR Review Comment: https://git.openjdk.org/jdk/pull/23748#discussion_r1971142347