RFR: 8342881: RISC-V: secondary_super_cache does not scale well: C1 and interpreter [v6]

[Fei Yang]

On Wed, 11 Dec 2024 07:23:18 GMT, Gui Cao <gcao at openjdk.org> wrote:

>> Follow this patch https://github.com/openjdk/jdk/pull/19989, The fix for [JDK-8332587](https://bugs.openjdk.org/browse/JDK-8332587) was for C2 only. Implement the same fix for C1 and the interpreter.
>> 
>> ### Testing
>> - [x] Run tier1-3 tests on SOPHON SG2042 (release)
>
> Gui Cao has updated the pull request incrementally with one additional commit since the last revision:
> 
>   Update code comment

src/hotspot/cpu/riscv/macroAssembler_riscv.hpp line 954:

> 952:   void revb(Register Rd, Register Rs, Register tmp1 = t0, Register tmp2 = t1);  // reverse bytes in doubleword
> 953: 
> 954:   void ror_reg(Register dst, Register src, Register shift, Register tmp = t0);

Hi, Could you please merge master? Then we can rename this routine to:
`void ror(Register dst, Register src, Register shift, Register tmp = t0);`

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PR Review Comment: https://git.openjdk.org/jdk/pull/21922#discussion_r1908629206