RFR: 8347352: RISC-V: Cleanup bitwise AND assembler routines

[Fei Yang]

On Sun, 12 Jan 2025 03:00:35 GMT, Feilong Jiang <fjiang at openjdk.org> wrote:

>> Hi, Please consider this small refactoring work.
>> 
>> It's a bit strange that we have `Assembler::_and_imm12` and `MacroAssembler::andi`, which is quite different from friends `Assembler::ori` and `Assembler::xori`. And it doesn't seem necessary to have this `MacroAssembler::andi` which checks the immediate range. I find the immediate is within signed 12-bit range for most of the cases. One exception is in file `sharedRuntime_riscv.cpp` where I think we can do `mv` + `andr` instead.
>> 
>> Testing on linux-riscv64:
>> - [x] tier1-3 and gtest:all (release)
>> - [x] hotspot:tier1 (fastdebug)
>
> Looks more consistent now, thanks!

@feilongjiang : Thanks for the review! Could we have a Reviewer please? Maybe @Hamlin-Li @robehn ?

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PR Comment: https://git.openjdk.org/jdk/pull/23008#issuecomment-2588891937