RFR: 8359965: Enable paired pushp and popp instruction usage for APX enabled CPUs [v2]

[Jatin Bhateja]

On Tue, 8 Jul 2025 22:44:55 GMT, Srinivas Vamsi Parasa <sparasa at openjdk.org> wrote:

>> The goal of this PR is to enhance the existing x86 assembly stubs using PUSH and POP instructions with paired PUSHP/POPP instructions which are part of Intel APX technology.
>> 
>> In Intel APX, the PUSHP and POPP instructions are modern, compact replacements for the legacy PUSH and POP, designed to work seamlessly with the expanded set of 32 general-purpose registers (R0–R31). Unlike their predecessors, they use the new APX (REX2-based) encoding, enabling more uniform and efficient instruction formats. These instructions improve code density, simplify register access, and are optimized for performance on APX-enabled CPUs.
>> 
>> Pairing PUSHP and POPP in Intel APX provides CPU-level benefits such as more efficient instruction decoding, better stack pointer tracking, and improved register dependency management. Their uniform encoding allows for streamlined execution, reduced pipeline stalls, and potential micro-op fusion, all of which enhance performance and power efficiency. This pairing helps the processor optimize speculative execution and register lifetimes, making code faster and more scalable on modern architectures.
>
> Srinivas Vamsi Parasa has updated the pull request incrementally with one additional commit since the last revision:
> 
>   rename to paired_push and paired_pop

src/hotspot/cpu/x86/gc/z/zBarrierSetAssembler_x86.cpp line 114:

> 112:         __ paired_push(rax);
> 113:       }
> 114:       __ paired_push(rcx);

Hi @vamsi-parasa , for consecutive push/pop we can use push2/pop2 and 16byte alignment can be  guaranteed using following technique 
https://github.com/openjdk/jdk/pull/25351/files#diff-d5d721ebf93346ba66e81257e4f6c5e6268d59774313c61e97353c0dfbf686a5R94

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PR Review Comment: https://git.openjdk.org/jdk/pull/25889#discussion_r2204155927