RFR: 8359965: Enable paired pushp and popp instruction usage for APX enabled CPUs

[Srinivas Vamsi Parasa]

The goal of this PR is to enhance the existing x86 assembly stubs using PUSH and POP instructions with paired PUSHP/POPP instructions which are part of Intel APX technology.

In Intel APX, the PUSHP and POPP instructions are modern, compact replacements for the legacy PUSH and POP, designed to work seamlessly with the expanded set of 32 general-purpose registers (R0–R31). Unlike their predecessors, they use the new APX (REX2-based) encoding, enabling more uniform and efficient instruction formats. These instructions improve code density, simplify register access, and are optimized for performance on APX-enabled CPUs.

Pairing PUSHP and POPP in Intel APX provides CPU-level benefits such as more efficient instruction decoding, better stack pointer tracking, and improved register dependency management. Their uniform encoding allows for streamlined execution, reduced pipeline stalls, and potential micro-op fusion, all of which enhance performance and power efficiency. This pairing helps the processor optimize speculative execution and register lifetimes, making code faster and more scalable on modern architectures.

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Commit messages:
 - 8359965: Enable paired pushp and popp instruction usage for APX enabled CPUs

Changes: https://git.openjdk.org/jdk/pull/25889/files
  Webrev: https://webrevs.openjdk.org/?repo=jdk&pr=25889&range=00
  Issue: https://bugs.openjdk.org/browse/JDK-8359965
  Stats: 384 lines in 23 files changed: 20 ins; 0 del; 364 mod
  Patch: https://git.openjdk.org/jdk/pull/25889.diff
  Fetch: git fetch https://git.openjdk.org/jdk.git pull/25889/head:pull/25889

PR: https://git.openjdk.org/jdk/pull/25889