RFR: 8345298: RISC-V: Add riscv backend for Float16 operations - scalar [v5]

[Hamlin Li]

On Tue, 11 Mar 2025 11:00:55 GMT, Fei Yang <fyang at openjdk.org> wrote:

>> Hamlin Li has updated the pull request incrementally with two additional commits since the last revision:
>> 
>>  - clean
>>  - renaming
>
> src/hotspot/cpu/riscv/riscv.ad line 8346:
> 
>> 8344: instruct fma_HF_reg(fRegF dst, fRegF src1, fRegF src2)
>> 8345: %{
>> 8346:   match(Set dst (FmaHF src2 (Binary dst src1)));
> 
> Question: Why is `dst` used as one of the source operands at the same time? There doesn't seem to be such a constraint at the instruction level. I didn't see similar constraint for F/D variants `maddF_reg_reg` and `maddD_reg_reg`. So it's likely to be relaxed.

Yes, it make senses to me. Relaxed.

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PR Review Comment: https://git.openjdk.org/jdk/pull/23844#discussion_r1989169152