RFR: 8351666: [PPC64] Make non-volatile VectorRegisters available for C2 register allocation [v24]

[Martin Doerr]

On Fri, 2 May 2025 12:32:31 GMT, Martin Doerr <mdoerr at openjdk.org> wrote:

>> This PR makes the non-volatile VectorRegisters available for C2's register allocation.
>> 
>> I had to implement the VectorRegisters properly (4 VM Regs) like on other platforms. The old version has run into assertions and looked strange.
>> 
>> The non-volatile VectorRegisters are now saved when entering Java: call_stub and upcall_stubs.
>> I have rewritten the save and restore functions and used them for both. Then, I have removed code which has become dead. I only save and restore them if C2 uses the vector instructions (controlled by `SuperwordUseVSX`).
>> I have moved the non-volatile spill area out of the entry_frame_locals because it has a variable size, now.
>> 
>> The stack area for all non-volatile registers has become larger than the 288 Bytes which are allowed to be used below the SP (specified by the ABI). Therefore, I had to rewrite the call_stub sequence significantly. We need to push the new frame before saving the registers, now.
>> 
>> Saving and restoring the FP registers is not needed in the slow signature handler which also uses the save and restore code for non-volatile registers.
>> 
>> On Power10, we use vector pair instructions since Commit 8. E.g. in the call stub:
>> 
>>   0x000072c9483c07b4:   stxvp   vs52,-224(r2)
>>   0x000072c9483c07b8:   stxvp   vs54,-192(r2)
>>   0x000072c9483c07bc:   stxvp   vs56,-160(r2)
>>   0x000072c9483c07c0:   stxvp   vs58,-128(r2)
>>   0x000072c9483c07c4:   stxvp   vs60,-96(r2)
>>   0x000072c9483c07c8:   stxvp   vs62,-64(r2)
>> 
>> 
>> 
>>   0x000072c9483c0914:   lxvp    vs52,-224(r2)
>>   0x000072c9483c0918:   lxvp    vs54,-192(r2)
>>   0x000072c9483c091c:   lxvp    vs56,-160(r2)
>>   0x000072c9483c0920:   lxvp    vs58,-128(r2)
>>   0x000072c9483c0924:   lxvp    vs60,-96(r2)
>>   0x000072c9483c0928:   lxvp    vs62,-64(r2)
>
> Martin Doerr has updated the pull request with a new target base due to a merge or a rebase. The incremental webrev excludes the unrelated changes brought in by the merge/rebase. The pull request contains 35 additional commits since the last revision:
> 
>  - Improve readability of LXVX_OPCODE.
>  - Merge remote-tracking branch 'origin' into 8351666_PPC64_nv_VRs
>  - Add comment and clean up extra whitespaces.
>  - Merge remote-tracking branch 'origin' into 8351666_PPC64_nv_VRs
>  - Merge remote-tracking branch 'origin' into 8351666_PPC64_nv_VRs
>  - Make order of MachRegisters consistent with ConcreteRegisterImpl and simplify rc_class.
>  - Rewrite rc_class avoiding hard coded register numbers.
>  - Add comment regarding 8-Byte aligned stack slots for VecX.
>  - Add missing VSRs to RegisterSaver_LiveVSReg.
>  - Merge remote-tracking branch 'origin' into 8351666_PPC64_nv_VRs
>  - ... and 25 more: https://git.openjdk.org/jdk/compare/bb149349...e3cc8bcd

Thanks for the reviews!

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PR Comment: https://git.openjdk.org/jdk/pull/23987#issuecomment-2879318104