RFR: 8356159: RISC-V: Add Zabha

[Robbin Ehn]

On Thu, 15 May 2025 14:08:48 GMT, Robbin Ehn <rehn at openjdk.org> wrote:

> Hi, please consider.
> 
> This adds the byte and halfword atomic memory operations (Zabha) - https://github.com/riscv/riscv-zabha.
> All amo-instructions, except load-reserve and store-conditional, can also be performed on natural aligned half-words and bytes. (i.e. the extension do not add lr.h/b or sc.h/b) This includes amocas if zacas extension is present.
> 
> The majority of this patch is to support amocas.h/b. We are now starting to really feel the pain of all these extensions, as CAS:ing 16/8-bits can now be done in three different ways:
> - lr.w/sc.w 'narrow' CAS (no extension)
> - amocas.w 'narrow' CAS (Zacas)
> - amocas.h/b (Zacas + Zabha)
> 
> There is no hwprobe support yet.
> 
> Ran t1-3 with Zacas+Zabha and t1 without Zabha in qemu.
> 
> Thanks, Robbin

Yes, Rs2 is at 20->24 : https://riscv-software-src.github.io/riscv-unified-db/manual/html/isa/isa_20240411/insts/sc.w.html
We have several instruction where Rs1 and Rs2 have the wrong places.

I don't understand why this is not seen in the gtests, i.e. if there some issue here.

I'll investigat, thanks!

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PR Comment: https://git.openjdk.org/jdk/pull/25252#issuecomment-2890026656