RFR: 8356159: RISC-V: Add Zabha

[Fei Yang]

On Mon, 19 May 2025 11:09:16 GMT, Robbin Ehn <rehn at openjdk.org> wrote:

> > > Yes, Rs2 is at 20->24 : https://riscv-software-src.github.io/riscv-unified-db/manual/html/isa/isa_20240411/insts/sc.w.html We have several instruction where Rs1 and Rs2 have the wrong places.
> > 
> > 
> > I think I know what's going on here. The riscv spec says: `SC.W conditionally writes a word in rs2 to the address in rs1`. Even though the encoding of `rs1` and `rs2` doesn't look correct in jdk head, but the callers of `sc_w/d` still work by swapping the two params: address and new value. This means that you also need following addon changes in this PR:
> 
> That is why they are already swapped in signature:
> 
> ```
> void sc_w(Register Rd, Register Rs2, Register Rs1, Aqrl memory_order = aqrl)
> void NAME(Register Rd, Register Rs1, Register Rs2, Aqrl memory_order = relaxed)
> ```
> 
> Otherwise gtests wouldn't work.

Ah, I see. Maybe it's better to change the caller's param passing to reflect this?
But I still don't understand the performance impact here. I suppose that changing the default memory ordering won't make a difference here?  Because I see no one uses the default value for now.

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PR Comment: https://git.openjdk.org/jdk/pull/25252#issuecomment-2890681604