RFR: 8356159: RISC-V: Add Zabha [v5]

[Robbin Ehn]

On Fri, 23 May 2025 03:25:39 GMT, Fei Yang <fyang at openjdk.org> wrote:

>> Robbin Ehn has updated the pull request with a new target base due to a merge or a rebase. The incremental webrev excludes the unrelated changes brought in by the merge/rebase. The pull request contains nine additional commits since the last revision:
>> 
>>  - Review comments
>>  - Merge branch 'master' into 8356159
>>  - Review fix
>>  - Bug and review fixes
>>  - Merge branch 'master' into 8356159
>>  - Revert back to default relaxed
>>  - Merge branch 'master' into 8356159
>>  - Fixed ws
>>  - Initial draft
>
> src/hotspot/cpu/riscv/riscv.ad line 5257:
> 
>> 5255: %}
>> 5256: 
>> 5257: instruct compareAndSwapB(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval, rFlagsReg cr)
> 
> Like `compareAndSwapI` and `compareAndSwapL`, I don't think we need to make `oldval` or `newval` fixed registers for `compareAndSwapB`. We can remove this constraint and there's no need to list `cr`. I mean this:
> 
> instruct compareAndSwapB(iRegINoSp res, indirect mem, iRegI oldval, iRegI newval)
> 
> Similar for `compareAndSwapBAcq`, `compareAndSwapS`, `compareAndSwapSAcq` and the weak variants.

Good find, thank you!

> src/hotspot/cpu/riscv/riscv.ad line 5623:
> 
>> 5621: %}
>> 5622: 
>> 5623: instruct compareAndExchangeB(iRegINoSp res, indirect mem, iRegI_R12 oldval, iRegI_R13 newval, rFlagsReg cr)
> 
> Similar here. No need to make `oldval` or `newval` fixed registers for `compareAndExchangeB`, `compareAndExchangeS`, `compareAndExchangeBAcq` or `compareAndExchangeSAcq`. And we should also remove `cr` which is not used.

Good find, thank you!

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PR Review Comment: https://git.openjdk.org/jdk/pull/25252#discussion_r2106829154
PR Review Comment: https://git.openjdk.org/jdk/pull/25252#discussion_r2106829399