RFR: 8365147: AArch64: Replace DMB + LD + DMB with LDAR for C1 volatile field loads [v3]

[Andrew Haley]

On Wed, 12 Nov 2025 11:09:45 GMT, Samuel Chee <duke at openjdk.org> wrote:

>> Replaces the DMB ISH + LD + DMB ISHLD sequence with LDAR for volatile field loads - for example, AtomicLong::get.
>> 
>> This is valid, as originally the DMBs were necessary due to the case described here - https://bugs.openjdk.org/browse/JDK-8179954. As in the rare case where the LD can be reordered with an LDAR or STLR from the C2 implementation for stores and loads, these DMBs are required.
>> However, acquire/release operations use a sequentially consistent model which does not allow reordering between them. Hence, the LD can be replaced with an LDAR to disallow reordering with a STLR/LDAR and the first DMB can be removed.
>> 
>> The LDAR has acquire semantics, so it's impossible for memory accesses after to be reordered before; the DMB ISHLD is not required. Therefore, a singular LDAR is sufficient.
>
> Samuel Chee has updated the pull request with a new target base due to a merge or a rebase. The pull request now contains five commits:
> 
>  - Address review comments. Refine.
>    
>    Change-Id: I9cc0308300548c1892d39791e00b41ef13c95e63
>  - Merge from the main branch
>  - Address review comments
>    
>    Change-Id: Ica13be8094ac0f057066042ef0a5ec5927b98dfd
>  - Refine code generation for mem2reg_volatile
>    
>    The patch is contributed by @theRealAph.
>    
>    Change-Id: I7ab1854dd238cdce72a4ab218b5b4ee84ad39586
>  - 8365147: AArch64: Replace DMB + LD + DMB with LDAR for C1 volatile loads
>    
>    Replaces the DMB ISH + LD + DMB ISHLD sequence with LDAR
>    for volatile field loads - for example, AtomicLong::get.
>    
>    This is valid, as originally the DMBs were necessary due to
>    the case described here - https://bugs.openjdk.org/browse/JDK-8179954.
>    As in the rare case where the LD can be reordered with an LDAR
>    or STLR from the C2 implementation for stores and loads, these
>    DMBs are required.
>    However, acquire/release operations use a sequentially consistent model
>    which does not allow reordering between them. Hence, the LD can be
>    replaced with an LDAR to disallow reordering with a STLR/LDAR
>    and the first DMB can be removed.
>    
>    The LDAR has acquire semantics, so it's impossible for
>    memory accesses after to be reordered before; the DMB ISHLD is
>    not required. Therefore, a singular LDAR is sufficient.
>    
>    This excludes floats and doubles, as they do not have
>    equivalent load-acquire instructions.
>    
>    Change-Id: Ia93607f8bb20c2d974fe6b2e586dd3239bb2728c

src/hotspot/cpu/aarch64/c1_LIRAssembler_aarch64.cpp line 948:

> 946: }
> 947: 
> 948: void LIR_Assembler::load_generic(LIR_Address *from_addr, LIR_Opr dest,

Suggestion:

void LIR_Assembler::load_relaxed(LIR_Address *from_addr, LIR_Opr dest,

Standard terminology.

-------------

PR Review Comment: https://git.openjdk.org/jdk/pull/26748#discussion_r2517938298