RFR: 8371649: ZGC: AArch64: redundant OrderAccess::fence in ZBarrierSetAssembler::patch_barrier_relocation

[Andrew Haley]

On Wed, 12 Nov 2025 22:22:29 GMT, Erik Österlund <eosterlund at openjdk.org> wrote:

> The way I look at it, the fence was there for hardware that is unsophisticated enough to require manual cache flushing instead of having cache coherency that understands instruction edits, and at the same time has unsophisticated enough fences that are not speculated across such that the buffered store hits the cache before invalidating the cache, and not after, which would be awkward.

Understood. But there are two caches, and `OrderAccess::fence` does not affect icache. So `OrderAccess::fence` cannot do anything to help. in order to make sure the buffered store hits the icache we need `DSB; ISB`, which  `OrderAccess::fence` does.

On the other hand, the cost of `OrderAccess::fence` is small in comparison with `ICache::invalidate_word`, so there's a question about why we're bothering to remove it.

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PR Comment: https://git.openjdk.org/jdk/pull/28244#issuecomment-3526953448