RFR: 8370947: Mitigate Neoverse-N1 erratum 1542419 negative impact on GenZGC performance

[Evgeny Astigeevich]

On Thu, 20 Nov 2025 15:22:23 GMT, Axel Boldt-Christmas <aboldtch at openjdk.org> wrote:

>> Arm Neoverse N1 erratum 1542419: "The core might fetch a stale instruction from memory which violates the ordering of instruction fetches". It is fixed in Neoverse N1 r4p1.
>>  
>> Neoverse-N1 implementations mitigate erratum 1542419 with a workaround:
>> - Disable coherent icache.
>> - Trap IC IVAU instructions.
>> - Execute:
>>    - `tlbi vae3is, xzr`
>>    - `dsb sy`
>>  
>>  `tlbi vae3is, xzr` invalidates translations for all address spaces (global for address).  It waits for all memory accesses using in-scope old translation information to complete before it is considered complete.
>>  
>> As this workaround has significant overhead, Arm Neoverse N1 (MP050) Software Developer Errata Notice version 29.0 suggests:
>> 
>> "Since one TLB inner-shareable invalidation is enough to avoid this erratum, the number of injected TLB invalidations should be minimized in the trap handler to mitigate the performance impact due to this workaround."
>> 
>> This PR introduces a mechanism to defer instruction cache (ICache) invalidation for AArch64 to address the Arm Neoverse N1 erratum 1542419, which causes significant performance overhead if ICache invalidation is performed too frequently. The implementation includes detection of affected Neoverse N1 CPUs and automatic enabling of the workaround for relevant Neoverse N1 revisions.
>> 
>> Changes include:
>> 
>> * Added a new diagnostic JVM flag `NeoverseN1Errata1542419` to enable or disable the workaround for the erratum. The flag is automatically enabled for Neoverse N1 CPUs prior to r4p1, as detected during VM initialization.
>> * Introduced the `ICacheInvalidationContext` class to manage deferred ICache invalidation, with platform-specific logic for AArch64. This context is used to batch ICache invalidations, reducing performance impact. As the address for icache invalidation is not relevant, we use the nmethod's code start address.
>> * Provided a default (no-op) implementation for `ICacheInvalidationContext` on platforms where the workaround is not needed, ensuring portability and minimal impact on other architectures.
>> * Modified barrier patching and relocation logic (`ZBarrierSetAssembler`, `ZNMethod`, `RelocIterator`, and related code) to accept a `defer_icache_invalidation` parameter, allowing ICache invalidation to be deferred and later performed in bulk.
>> 
>> Benchmarking results: Neoverse-N1 r3p1 (Graviton 2)
>> 
>> - Baseline
>> 
>> $ taskset -c 0-3 java -Xbootclasspath/a:./wb.jar -XX:+UnlockDiagnosticVMOptions -XX:-NeoverseN1...
>
> I think the implementation is fine. We can always extend it later if we find that other platforms or hardware needs this sort of treatment.
> 
> My knowledge and experience with arm hardware implementation specifics are rather lacking. So I cannot comment on the validity of the assertions made here w.r.t. only invalidating the first instruction in the nmethod etc.
> 
> Hopefully some of our resident arm experts can chime in.

@xmas92

>  The added microbenchmark shows interesting regressions when an nmethod has no accesses to object's fields:
> 
> ```
> Benchmark                       Score     Error  Units
> GCPatchingNmethodCost.fullGC:base                       73.937 ±  17.764  ms/op
> GCPatchingNmethodCost.systemGC:base                     77.495 ±  11.963  ms/op
> GCPatchingNmethodCost.youngGC:base                      9.955 ±   1.649  ms/op
> GCPatchingNmethodCost.fullGC:fix                        88.865 ± 19.299  ms/op +20.1%
> GCPatchingNmethodCost.systemGC:fix                      90.572 ± 14.750  ms/op +16.9%
> GCPatchingNmethodCost.youngGC:fix                       10.219 ±  0.877  ms/op +2.7%
> ```

I think I might have an idea what causes the regressions. I'll be debugging it.

-------------

PR Comment: https://git.openjdk.org/jdk/pull/28328#issuecomment-3562960050