RFR: 8365290: [perf] x86 ArrayFill intrinsic generates SPLIT_STORE for unaligned arrays [v7]

[Vladimir Kozlov]

On Wed, 1 Oct 2025 19:41:41 GMT, Vladimir Ivanov <vaivanov at openjdk.org> wrote:

>> src/hotspot/cpu/x86/macroAssembler_x86.cpp line 5920:
>> 
>>> 5918:         if (EnableX86ECoreOpts) {
>>> 5919:             // align 'big' arrays to cache lines to minimize split_stores
>>> 5920:             cmpptr(count, 96 << shift);
>> 
>> What is `96?
>
> Two trends identified for buffer filling:
>  - filling up to cache line size by 4 bytes reduce performance;
>  - operate by cache line size improve performance.
> According to experiments on Xeon 6740E the 96 is good compromise. For small arrays it is better to ignore split_store and do filling by bigger elements.

What is cache line size for Xeon 6740E? That is what I am asking.

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PR Review Comment: https://git.openjdk.org/jdk/pull/26747#discussion_r2395856078