RFR: 8368722: RISC-V: Several vector load/store tests fail due to lack of support for misaligned vector access [v2]

[Dingli Zhang]

On Tue, 30 Sep 2025 03:01:10 GMT, Dingli Zhang <dzhang at openjdk.org> wrote:

>> Hi,
>> Can you help to review this patch? Thanks!
>> 
>> In `*VectorLoadStoreTests.java`,  `loadMemorySegmentMaskIOOBE` and `storeMemorySegmentMaskIOOBE` may fail because `int index = fi.apply((int) a.byteSize())` can generate random indices that result in misaligned addresses, leading to SIGBUS on hardware that disallows misaligned vector accesses.
>> 
>> Some RISC-V hardware supports fast misaligned scalar accesses but not vector ones, which causes SIGBUS when executing these tests with misaligned vector memory operations.
>> 
>> After [JDK-8368732](https://bugs.openjdk.org/browse/JDK-8368732), we can use `AlignVector` to check the result on platforms with or without fast misaligned vector accesses. When misaligned vector accesses are not supported, it is possible to completely disable the VM’s VectorAPI support by setting `EnableVectorSupport`, without affecting auto-vectorization.
>> 
>> In addition, after running fastdebug tests including `jdk_vector, jdk_vector_sanity, hotspot_vector_1, hotspot_vector_2, compiler/vectorapi, compiler/vectorization`, we found that some IR-related tests require EnableVectorSupport. Therefore, we added `@requires vm.opt.EnableVectorSupport == true` to skip these tests.
>> 
>> We can check the status of EnableVectorSupport as follows:
>> 
>> On k1
>> $ java --add-modules=jdk.incubator.vector -Xlog:compilation -version
>> [0.737s][info][compilation] EnableVectorSupport=false
>> [0.738s][info][compilation] EnableVectorReboxing=false
>> [0.738s][info][compilation] EnableVectorAggressiveReboxing=false
>> 
>> On qemu
>> $ java --add-modules=jdk.incubator.vector -Xlog:compilation -version
>> [3.048s][info][compilation] EnableVectorSupport=true
>> [3.050s][info][compilation] EnableVectorReboxing=true
>> [3.051s][info][compilation] EnableVectorAggressiveReboxing=true
>> 
>> 
>> ### Test (fastdebug)
>> - [x] Run jdk_vector, jdk_vector_sanity, hotspot_vector_1, hotspot_vector_2, compiler/vectorapi, compiler/vectorization on k1
>
> Dingli Zhang has updated the pull request with a new target base due to a merge or a rebase. The incremental webrev excludes the unrelated changes brought in by the merge/rebase. The pull request contains one additional commit since the last revision:
> 
>   8368722: RISC-V: Several vector load/store tests fail without support for misaligned vector access

> I'm not quite sure, but seems this is not an issue only on riscv? It might be better to get more attention from other developers working on other platforms, could you modify the subject of this bug/pr? Sorry for previous suggestion to change the subject name.

Hi, @Hamlin-Li  Sorry for the late reply. I have modified this check following the suggestion of @iwanowww.


> BTW, I see more tests using jdk.incubator.vector besides of tests under test/hotspot/jtreg/compiler/vectorapi, like this test. Could they also face the similar issue?

I don't think they will have similar issues. If they do IR test on places where jdk.incubator.vector is used,
it would be caught by my local tier1-tier3 tests on linux-riscv64 RVV platform with fastdebug build.

> `AlignVector` doesn't look appropriate here (and in other places). If hardware doesn't support misaligned vector accesses, then there shouldn't be a way to set `AlignVector = false`. The JVM should issue a warning and unconditionally set both `EnableVectorSupport = false` and `AlignVector = true` irrespective of what is specified on the command line.

Hi @iwanowww  Make sense. I have added checking for that in my latest commit. Please take another look.

> Also, the problem is not specific to C2. There are vectorized VM stubs which can be affected by absence of hardware misaligned vector access support.
>
> I suggest to introduce a cross-platform `VM_Version::supports_misaligned_vector_accesses()` which affects `AlignVector`, `EnableVectorSupport`, `AvoidUnalignedAccesses` (maybe even supersedes it?), and eventually all usages of vector memory accesses in VM code.
>

Good suggestion. I have modified accordingly.
At the RISC-V Linux kernel level, there is a distinguishment for support for misaligned vector and scalar access.
Check the hwprobe linux syscall (`RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERF` vs `RISCV_HWPROBE_KEY_MISALIGNED_VECTOR_PERF`) [1].
We set `AlignVector` and `EnableVectorSupport` to `true` and `false` respectively if we don't have fast misaligned vector access.
And we set `AvoidUnalignedAccesses` and `UseUnalignedAccesses` to `true` and `false` respectively if we don't have fast misaligned scalar access.

[1] https://docs.kernel.org/arch/riscv/hwprobe.html

> Speaking of aligned/misaligned vector accesses, does RISC-V distinguish them on ISA level (with different instructions)? If that's the case, then it makes sense to add asserts in corresponding Assembler/MacroAssembler methods.

No. There is not such a distinguish from the RISC-V Vector Spec.

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PR Comment: https://git.openjdk.org/jdk/pull/27506#issuecomment-3384847342
PR Comment: https://git.openjdk.org/jdk/pull/27506#issuecomment-3384857124